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Computer Architecture Group


PARADISE++ is an open-source comprehensive methodology to evaluate emerging technologies with a vertical simulation flow from the individual device level all the way up to the architectural level.


Superconducting Race Logic Accelerators

The aim of this project is to make computation in superconducting circuits as efficient as possible by re-using computing architectures inspired by traditional technologies into superconducting logic.

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Mobiliti is a proof-of-concept, scalable transportation system simulator that implements parallel discrete event simulation on high-performance computers



The PINE interconnect (Photonically Interconnected datacenter Elements) allows compute, memory or storage modules to be flexibly combined through one-model-fits-all embedded photonic connectivity and b...



Open2C aims to provide a powerful yet flexible and easy-to-extend tool that enables exploring coherent cache memory subsystem for upcoming large-scale computing systems.



To pave the way towards future quantum accelerators adoption, we propose to define several abstraction levels throughout the entire control hardware stack that starts with comprehensive software-hardw...



The Computer Architecture Group is focused on delivering continued increases in performance to all scientific application areas through the development, programming, and utilization of advanced computing architectures. These architectures may be deployed anywhere within a scientific workflow - spanning from within an HPC data center to edge computing devices deployed remotely in the field. In addition, we seek to bring HPC tools and techniques to new application areas ranging from biosciences to transportation models.




In this project, we propose to build a post-Moore HPC (High-Performance Computing) system simulation framework to enable large scale simulations of post-Moore architectures built using emerging devices and technologies. With the HPC systems…

Superconducting Race Logic Accelerators

The aim of this project is to make computation in superconducting circuits, circuits that operate around 4K temperatures and have close to zero resistance, as efficient as possible. Many approaches today try to re-use computing architectures (the…

DFT Beyond Moore’s Law: Extreme Hardware Specialization for the Future of HPC

The project goal is to demonstrate the performance potential of purpose-built architectures as potential future for HPC applications in absence of Moore’s Law. Our approach is to reformulate the LS3DF algorithm to make it amenable to specialized…

Project 38

Project 38 is a set of vendor-agnostic architectural explorations involving DOD, the DOE Office of Science, and NNSA (these latter two organizations are referred to below as “DOE”). These explorations are expected to accomplish the following:…
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iARPA SuperTools

The Intelligence Community (IC) is well known to be a major consumer of high performance computing, but is increasingly finding itself frustrated by limitations in overall power consumption and clock speed. The amazing successes of semiconductor…

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Towards Automated Superconducting Circuit Calibration using Deep Reinforcement Learning

August 23, 2021

Experiences Porting the SU3_Bench Microbenchmark to the Intel Arria 10 and Xilinx Alveo U280 FPGAs

April 26, 2021

Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization

December 1, 2020

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