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David Donofrio
Biographical Sketch
After earning his degree in Computer Engineering at Virginia Tech, David spent several years at Intel in graphics hardware architecture. He led the Computer Architecture Group at Lawrence Berkeley National Lab until October 2019. His research interests are focused on the design and simulation of future exascale systems with a focus on processor architecture.
Current Projects
- iARPA SuperTools
- Open2C: Open Cache Coherency
- OpenSoC Fabric: An Open-Source Network-On-Chip Generator
- Project 38: A set of vendor-agnostic architectural explorations involving NSA, the DOE Office of Science, and NNSA
- VTE: Verilator Testbench Environment
Journal Articles
K. E. Bouchard, J.B. Aimone, M. Chun, T. Dean, M. Denker, M. Diesmann, D. Donofrio, L.M. Frank, N. Kasthuri, C. Koch, O. Rübel, H. Simon, F. T. Sommer, Prabhat, "International Neuroscience Initiatives Through the Lens of High-Performance Computing", IEEE Computer, April 12, 2018, 51(4):50-59, doi: doi 10.1109/MC.2018.2141039
K. E. Bouchard, J, B. Aimone, M. Chun, T. Dean, M. Denker, M. Diesmann, D. D. Donofrio, L. M. Frank, N. Kasthuri, C. Koch, O. Rübel, H. D. Simon, F. T. Sommer, Prabhat, "High-Performance Computing in Neuroscience for Data-Driven Discovery, Integration, and Dissemination", Neuron, November 2, 2016, 92(3):628-631, doi: http://dx.doi.org/10.1016/j.neuron. 2016.10.035
Conference Papers
Anastasiia Butko, George Michelogiannakis, Samuel Williams, Costin Iancu, David Donofrio, John Shalf, Jonathan Carter, Irfan Siddiqi, "Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization", IEEE Conference on Rebooting Computing (ICRC), December 2020,
- Download File: ICRC20-QUASAR-final.pdf (pdf: 1.1 MB)
Anastasiia Butko, George Michelogiannakis, David Donofrio, John Shalf, "Extending classical processors to support future large scale quantum accelerators", Proceedings of the 16th ACM International Conference on Computing Frontiers Pages, April 2019,
Anastasiia Butko, George Michelogiannakis, David Donofrio, John Shalf, "TIGER: topology-aware task assignment approach using ising machines", Proceedings of the 16th ACM International Conference on Computing Frontiers, April 2019,
D Vasudevan, G Michclogiannakis, D Donofrio, J Shalf, "PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments", 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), IEEE, January 2019, doi: 10.1109/ispass.2019.00022
Anastasiia Butko, Albert Chen, David Donofrio, Farzad Fatollahi-Fard, John Shalf, "Open2C: Open-source Generator for Exploration of Coherent Cache Memory Subsystems", MEMSYS '18, New York, NY, USA, ACM, 2018, 311--317, doi: 10.1145/3240302.3270314
D Vasudevan, A Butko, G Michelogiannakis, D Donofrio, J Shalf, "Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies", Springer International Publishing, January 1, 2017, 115--123, doi: 10.1007/978-3-319-67630-2_10
With the decline and eventual end of historical rates of lithographic scaling, we arrive at a crossroad where synergistic and holistic decisions are required to preserve Moore's law technology scaling. Numerous emerging technologies aim to extend digital electronics scaling of performance, energy efficiency, and computational power/density,
ranging from devices (transistors), memories, 3D integration capabilities, specialized architectures, photonics, and others.
The wide range of technology options creates the need for an integrated strategy to understand the impact of these emerging technologies on future large-scale digital systems for diverse application requirements and optimization metrics.
In this paper, we argue for a comprehensive methodology that spans the different levels of abstraction -- from materials, to devices, to complex digital systems and applications. Our approach integrates compact models of low-level characteristics of the emerging technologies to inform higher-level simulation models to evaluate their responsiveness to application requirements.
The integrated framework can then automate the search for an optimal architecture using available emerging technologies to maximize a targeted optimization metric.
George Michelogiannakis, Dave Donofrio, John Shalf, "Modeling of Novel Transistors, Manufacturing Technologies, and Architectures to Preserve Digital Computing Performance Scaling", 1ST INTERNATIONAL WORKSHOP ON POST-MOORE’S ERA SUPERCOMPUTING (PMES), November 2016,
- Download File: pmes.pdf (pdf: 103 KB)
Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf, "OpenSoC Fabric: On-Chip Network Generator", ISPASS 2016: International Symposium on Performance Analysis of Systems and Software, IEEE, April 2016, 194-203, doi: 10.1109/ISPASS.2016.7482094
Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf, "OpenSoC Fabric: On-Chip Network Generator", Proceedings of the Workshop on Network on Chip Architectures, ACM, December 2014, 45-50, LBNL LBNL-1005675, doi: 10.1145/2685342.2685351
- Download File: opensocnocarc.pdf (pdf: 1.1 MB)
Book Chapters
John Shalf, Donofrio, Rowen, Oliker, Michael F. Wehner, "Green Flash: Climate Machine (LBNL)", Encyclopedia of Parallel Computing, (Springer: 2010) Pages: 809-819
Green Flash is a research project focused on an application-driven manycore chip design that leverages commodity-embedded circuit designs and hardware/software codesign processes to create a highly programmable and energy-efficient HPC design. The project demonstrates how a multidisciplinary hardware/software codesign process that facilitates close interactions between applications scientists, computer scientists, and hardware engineers can be used to develop a system tailored for the requirements of scientific computing.
Presentation/Talks
George Michelogiannakis, David Donofrio, John Shalf, Modeling of Novel Transistors, Manufacturing Technologies, and Architectures to Preserve Digital Computing Performance Scaling, Post-Moore's Era Supercomputing (PMES) Workshop, November 2016,
- Download File: PMES-2016.pptx (pptx: 4.5 MB)
Reports
George Michelogiannakis, John Shalf, David Donofrio, John Bachan,, "Continuing the Scaling of Digital Computing Post Moore’s Law", LBNL report, April 2016, LBNL 1005126,
The approaching end of traditional CMOS technology scaling that up until now followed Moore's law is coming to an end in the next decade. However, the DOE has come to depend on the rapid, predictable, and cheap scaling of computing performance to meet mission needs for scientific theory, large scale experiments, and national security. Moving forward, performance scaling of digital computing will need to originate from energy and cost reductions that are a result of novel architectures, devices, manufacturing technologies, and programming models. The deeper issue presented by these changes is the threat to DOE’s mission and to the future economic growth of the U.S. computing industry and to society as a whole. With the impending end of Moore’s law, it is imperative for the Office of Advanced Scientific Computing Research (ASCR) to develop a balanced research agenda to assess the viability of novel semiconductor technologies and navigate the ensuing challenges. This report identifies four areas and research directions for ASCR and how each can be used to preserve performance scaling of digital computing beyond exascale and after Moore's law ends.
