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Computer Architecture Group

Farzad Fatollahi-Fard

Farzad Fatollahi Fard
Farzad Fatollahl-Fard
FPGA Computer Systems Engineer
Computer Science Department
Phone: 510-486-4480
Mobile: 415-625-3935
Computer Architecture Group
One Cyclotron Road
Mail Stop #59R4104
Berkeley, CA 94720 us

Biographical Sketch

Farzad Fatollahi-Fard is an FPGA Computing Systems Engineer in the Computer Architecture Group in the Computer Science Department at Lawrence Berkeley National Lab. He graduated from the University of California, Berkeley with a degree in Electrical Engineering and Computer Science. He spent several years designing FPGA platforms used in HPC applications for a startup company prior to coming the Lab. His research interests are focused on application co-design, custom HPC accelerators, and HPC on the edge.

Current Projects

  • iARPA AGILE: Advanced Graphic Intelligence Logical Computing Environment
  • iARPA SuperTools
  • Project 38: A set of vendor-agnostic architectural explorations involving NSA, the DOE Office of Science, and NNSA

Past Projects

Conference Papers

Douglas Doerfler, Farzad Fatollahi-Fard, Colin MacLean, Tan Nguyen, Samuel Williams, Nicholas J. Wright, Marco Siracusa, "Experiences Porting the SU3_Bench Microbenchmark to the Intel Arria 10 and Xilinx Alveo U280 FPGAs", International Workshop on OpenCL (iWOCL), April 2021, doi: 10.1145/3456669.3456671

Anastasiia Butko, Albert Chen, David Donofrio, Farzad Fatollahi-Fard, John Shalf, "Open2C: Open-source Generator for Exploration of Coherent Cache Memory Subsystems", MEMSYS '18, New York, NY, USA, ACM, 2018, 311--317, doi: 10.1145/3240302.3270314

Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf, "OpenSoC Fabric: On-Chip Network Generator", ISPASS 2016: International Symposium on Performance Analysis of Systems and Software, IEEE, April 2016, 194-203, doi: 10.1109/ISPASS.2016.7482094

Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf, "OpenSoC Fabric: On-Chip Network Generator", Proceedings of the Workshop on Network on Chip Architectures, ACM, December 2014, 45-50, LBNL LBNL-1005675, doi: 10.1145/2685342.2685351