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Computer Architecture Group

Darren Lyles

Darren Lyles
Computer Science Department
Computer Architecture Group

Biographical Sketch

Darren is a Hardware Engineer in the Computer Architecture Group (CAG) in the Computational Research Division (CRD) at Lawrence Berkeley National Laboratory. His current work focuses on the design, testing, verification, and application of superconducting race logic circuits and the design and testing of Electronic Design Automation (EDA) tools that support superconducting designs.

Darren graduated from the University of California, Berkeley with a degree in Electrical Engineering and Computer Science (EECS). Prior to joining the laboratory, he worked on the design, verification, and evaluation of various Field Programmable Gate Array (FPGA) components.

Current Projects

Conference Papers

Meriam Gay Bautista, Patricia Gonzalez-Guerrero, Darren Lyles, Kylie Huch, George Michelogiannakis, "Superconducting Digital DIT Butterfly Unit for Fast Fourier Transform Using Race Logic", 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS), IEEE, June 2022, 441-445,

Patricia Gonzalez-Guerrero, Meriam Gay Bautista, Darren Lyles, George Michelogiannakis, "Temporal and SFQ Pulse-Streams Encoding for Area-Efficient Superconducting Accelerators", 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’22), ACM, February 2022,

Meriam Gay Bautista, Patricia Gonzalez-Guerrero, Darren Lyles, George Michelogiannakis, "Superconducting Shuttle-flux Shift Buffer for Race Logic", 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2021,

George Michelogiannakis, Darren Lyles, Patricia Gonzalez-Guerrero, Meriam Bautista, Dilip Vasudevan, Anastasiia Butko, "SRNoC: A Statically-Scheduled Circuit-Switched Superconducting Race Logic NoC", IEEE International Parallel and Distributed Processing Symposium (IPDPS), May 2021,