CRD Staff Get Funding for Post-Moore’s Law Computing Research

George Michelogiannakis and Dilip Vasudevan, research scientists in Berkeley Lab’s Computational Research Division (CRD), have been awarded funding from the Army Research Office for two post-Moore’s Law computing research projects. The funding comes from the Department of Defense’s Advanced Computing Initiative.

Michelogiannakis’ award is $1 million per year for three years, with about $350,000 of that going to collaborators at UC Santa Barbara. The focus of project, which is scheduled to start October 1, is superconducting race logic accelerators.

Creating computing systems that address areas of strategic importance to U.S. national security policy well beyond the end of traditional CMOS transistor scaling will require truly novel methods of computing, Michelogiannakis noted.  This project will design race-logic superconducting accelerators to achieve multiple orders of magnitude higher performance per unit power for high performance computing (HPC) and national intelligence applications. It will also leverage and extend existing tools and libraries to be able to model larger-scale superconducting circuits with adequate accuracy.

“As we look past CMOS there is no reason to think that those same abstractions best serve to encapsulate the computational potential inherent to emerging devices,” Michelogiannakis said. “This project will establish a new and radically more efficient foundation for computation at the intersection of superconducting circuits and delay-coded computation.”

Dilip Vasudevan

Starting in October, Vasudevan will receive $1.2 million over three years for his project, “PARADISE++: Large Scale Optimistic Synchronization based Simulation of Post-Moore Systems.” This research is a spin-off from a Berkeley Laboratory Directed Research and Development (LDRD) award for PARADISE. The goal of this work is to develop a large-scale system simulation framework that will support the simulation of future supercomputing systems built with new transistor and memory devices.

“With HPC performance reaching exaflops and transistor scaling reaching the saturation point, HPC systems built for the post Moore era are evolving to extremely heterogeneous systems,” he said. “New computing, memory, interconnect, and storage models are needed to reach the expected performance and energy benefits.”

Toward this end, Vasudevan’s team will investigate the performance of optimistic synchronization in the domain of highly heterogeneous and asynchronous computer architectural simulations, extending the PARADISE tool flow, which is a chip/ node level architectural simulator for post-Moore architectures to support large scale HPC system simulation using the optimistic synchronization based PDES simulation framework called Devastator. They will enhance the post-Moore models built in PARADISE to be used with the Devastator runtime and enable the large-scale (1000s of cores) simulation of post-Moore computing architectures at the HPC system level.