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Computer Architecture Group

Research

PINE

The cost and complexity of existing interconnects prevent designing datacenter racks tailored to emerging applications such as machine learning. The PINE interconnect (Photonically Interconnected datacenter Elements) allows compute, memory or storage modules to be flexibly combined through one-model-fits-all embedded photonic connectivity and better utilize distant resources. In addition, PINE allows system-level bandwidth to be reconfigured to better match application demands via bandwidth… Read More »

Continuing the Scaling of Digital Computing Post Moore’s Law

With the impending end of Moore’s law, it is imperative for the Office of Advanced Scientific Computing Research (ASCR) to develop a balanced research agenda to assess the viability of novel semiconductor technologies and navigate the ensuing challenges. Read More »

ProgrAMR

In order to model the behavior of AMR solvers that run in an asynchronous fashion, we have developed a tool that builds a skeleton task dependency graph for a variety of AMR algorithms.   The task dependency graph generated contains critical performance information, such as compute time estimates and required communication traffic volume.  The task graph exposes the true data dependencies of the constituent tasks and removes false dependencies that are often introduced as a byproduct of… Read More »

Project 38

Project 38 is a set of vendor-agnostic architectural explorations involving DOD, the DOE Office of Science, and NNSA (these latter two organizations are referred to below as “DOE”). These explorations are expected to accomplish the following: Near-term goal: Quantify the performance value and identify the potential costs of specific architectural concepts against a limited set of applications of interest to both the DOE and DOD. Long-term goal: Develop an enduring capability for DOE and DOD… Read More »

QUASAR Ice

To pave the way towards future quantum accelerators adoption, we propose to define several abstraction levels throughout the entire control hardware stack that starts with comprehensive software-hardware interface - quantum instruction set architecture (QUASAR). By extending RV32/64, QUASAR supports single- and dual-qubit gates (serial or parallel application), controlled measurement, bit manipulation, arbitrary phase rotation, and advanced pulse shaping. The first extended processor (QUASAR… Read More »

VTE

VTE is a library that allows fast and simple generation of C++ testers for modules written in Chisel and build an efficient interface to existing C++ based simulators. It contains Scala-based interface and C++ testbench class. Scala interface interacts with Firtl Interpreter and generates a basic set of C++ testbench files. These files contain the list of the Device Under Test (DUT) input-output ports as well as their parameters. C++ testbench provides functionalities similar to the Chisel… Read More »