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Research

Characterization of DOE Mini-apps

The Computer Architecture Laboratory (CAL) will advance Exascale Design Space Exploration to develop energy efficient and effective processor and memory architecture R&D for DOE’s Exascale program. Read More »

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Continuing the Scaling of Digital Computing Post Moore’s Law

The approaching end of traditional CMOS technology scaling that up until now followed Moore's law is coming to an end in the next decade. However, the DOE has come to depend on the rapid, predictable, and cheap scaling of computing performance to meet mission needs for scientific theory, large scale experiments, and national security. Moving forward, performance scaling of digital computing will need to originate from energy and cost reductions that are a result of novel architectures, devices,… Read More »

Traffic Graph

Mobiliti

Overview Transportation systems are becoming increasingly complex with the evolution of emerging technologies, including deeper connectivity and automation, which will require more advanced control mechanisms for efficient operation (in terms of energy, mobility, and productivity).Stakeholders, including government agencies, industry, and local populations, all have an interest in efficient outcomes, yet there are few tools for developing a holistic understanding of urban… Read More »

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Mota Mapper

Mota is a library that provides several heuristics for the purpose of AMR task placement.  It is multi-objective in the sense that it simultaneously balances the computational load on each rank as well as the communication traffic between the boxes.  We are investigating a variety of approaches to do the task placement and utilizing modeling and simulation tools to evaluate these approaches.  The heuristics used for mapping include algorithms such as greedy list assignment and space-filling… Read More »

Open2C

This project aims to deliver the coherent multilevel cache hierarchy as a part of the Open System Architect project. Read More »

NoC Abstract

OpenSoC Fabric

Abstract Recent advancements in technology scaling have shown a trend towards greater integration with large-scale chips containing thousands of processors connected to memories and other I/O devices using non-trivial network topologies. Software simulation proves insufficient to study the tradeoffs in such complex systems due to slow execution time, whereas hardware RTL development is too time-consuming. We present OpenSoC Fabric, an on-chip network generation infrastructure which aims to… Read More »

AMR

ProgrAMR

In order to model the behavior of AMR solvers that run in an asynchronous fashion, we have developed a tool that builds a skeleton task dependency graph for a variety of AMR algorithms.   The task dependency graph generated contains critical performance information, such as compute time estimates and required communication traffic volume.  The task graph exposes the true data dependencies of the constituent tasks and removes false dependencies that are often introduced as a byproduct of… Read More »

VTE

Abstract VTE is a library that allows fast and simple generation of C++ testers for modules written in Chisel and build an efficient interface to existing C++ based simulators. It contains Scala-based interface and C++ testbench class. Scala interface interacts with Firtl Interpreter and generates a basic set of C++ testbench files. These files contain the list of the Device Under Test (DUT) input-output ports as well as their parameters. C++ testbench provides functionalities similar to the… Read More »