Tan Nguyen is a research scientist at Lawrence Berkeley National Laboratory. Nguyen's research focuses on performance analysis and code optimizations for various processor architectures, including multi- and many-core CPUs, GPUs, and FPGAs. He is also interested in compiler analysis and code generation, programming models and runtime systems for large-scale applications.
Nguyen received his Ph.D. degree in Computer Science from University of California, San Diego in 2014. Nguyen is an alumnus of the Vietnam Education Foundation.
- ECP-Hardware Evaluation: Use Performance Analysis Tools to predict application performance on future DOE's systems
- NERSC10: Explore alternative processor architectures for the next generation of supercomputer at NERSC
- AMReX: Optimize Massively Parallel, Block-structured Adaptive Mesh Refinement (AMR) Applications
- Collaborative research activities: scalable AI algorithms, Graph Neural Networks
- ExaSAT: An Exascale Static Analysis Tool for Hardware/Software Design Space Evaluation
Weiqun Zhang, Ann Almgren, Vince Beckner, John Bell, Johannes Blashke, Cy Chan, Marcus Day, Brian Friesen, Kevin Gott, Daniel Graves, Max P. Katz, Andrew Myers, Tan Nguyen, Andrew Nonaka, Michele Rosso, Samuel Williams, Michael Zingale, "AMReX: a framework for block-structured adaptive mesh refinement", Journal of Open Source Software, May 2019, doi: 10.21105/joss.01370
Tan Nguyen, Pietro Cicotti, Eric Bylaska, Dan Quinlan, and Scott Baden, "Automatic Translation of MPI Source into a Latency-tolerant, Data-driven Form", Journal of Parallel and Distributed Computing, February 21, 2017,
Weiqun Zhang, Ann Almgren, Marcus Day, Tan Nguyen, John Shalf, Didem Unat, "BoxLib with Tiling: An AMR Software Framework", SIAM Journal on Scientific Computing, 2016,
Tan Nguyen, Daniel Hefenbrock, Jason Oberg, Ryan Kastner and Scott Baden, "A software-based dynamic-warp scheduling approach for load-balancing the Viola-Jones face detection algorithm on GPUs", Journal of Parallel and Distributed Computing, January 31, 2013,
Douglas Doerfler, Farzad Fatollahi-Fard, Colin MacLean, Tan Nguyen, Samuel Williams, Nicholas J. Wright, Marco Siracusa, "Experiences Porting the SU3_Bench Microbenchmark to the Intel Arria 10 and Xilinx Alveo U280 FPGAs", International Workshop on OpenCL (iWOCL), April 2021,
Tan Nguyen, Samuel Williams, Marco Siracusa, Colin MacLean, Douglas Doerfler, Nicholas J. Wright, "The Performance and Energy Efficiency Potential of FPGAs in Scientific Computing", (BEST PAPER) Performance Modeling, Benchmarking, and Simulation of High Performance Computer Systems (PMBS), November 2020,
- Download File: PMBS20-FPGA-final.pdf (pdf: 2.9 MB)