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A 32-bit RISC-V Core with Quantum Specific Extensions


To pave the way towards future quantum accelerators adoption, we propose to define several abstraction levels throughout the entire control hardware stack that starts with comprehensive software-hardware interface - quantum instruction set architecture (QUASAR). By extending RV32/64, QUASAR supports single- and dual-qubit gates (serial or parallel application), controlled measurement, bit manipulation, arbitrary phase rotation, and advanced pulse shaping. The first extended processor (QUASAR Ice) implements a 32-bit in-order 5-stage pipeline architecture with specialized quantum accelerator interface. This basic implementation supports up-to 512 qubit addressing, fast feedback loop and parallel gate execution.

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