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Computer Architecture Group


Open Cache Coherency


A cache-coherent memory subsystem plays an important role in complex digital computing systems. It maintains memory consistency across on-chip caches that hide the memory latency to improve computational performance. Being managed by hardware, the cache subsystem facilitates multi-core system programming and allows developers to focus on other crucial aspects. However, due to extensive protocol-related traffic and lack of explicit data movement management, cache memory scalability becomes a big concern. Existing evaluation techniques, such as cycle-approximate estimation or cycle-accurate simulation, do not guarantee accurate and fast results in the first case or require tremendous amount of efforts to implement and modify the system in the second.



We present Open Cache Coherence (Open2C). The project aims to provide a powerful yet flexible and easy-to-extend tool that enables exploring coherent cache memory subsystem for upcoming large-scale computing systems. Open2C includes a library of basic parameterized components that are required to build a complex coherent cache memory subsystem, such as miss register, TAG array, replacement policy unit, etc. The Open2C generator is written in Chisel language that allows each component to be accessed through provided methods in a functional and modular way. The generated system can be simulated using existing Chisel-based simulation tools or be compiled into the RTL and placed on FPGA for further evaluation. Open2C reduces the amount of effort researches spend on system implementation -- allowing them to focus on the protocol itself or a separate unit optimization.


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