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CAL: The Computer Architecture Laboratory

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CAL is a joint NNSA/SC activity involving Sandia National Laboratories (CAL-Sandia) and Lawrence Berkeley National Laboratory (CAL-Berkeley). The project advances Exascale Design Space Exploration to develop energy efficient and effective processor and memory architecture R&D for the Department of Energy's Exascale program. » Read More

Scaling Digital Computing Post Moore’s Law

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This report identifies four areas and research directions and how each can be used to preserve performance scaling of digital computing beyond exascale and after Moore's law ends. » Read More

Research

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Mota Mapper

Mota is a library that provides several heuristics for the purpose of AMR task placement.  It is multi-objective in the sense that it simultaneously balances the computational load on each rank as well as the communication traffic between the…
AMR

ProgrAMR

In order to model the behavior of AMR solvers that run in an asynchronous fashion, we have developed a tool that builds a skeleton task dependency graph for a variety of AMR algorithms.   The task dependency graph generated contains critical…
Rambutan TaskGraph

Rambutan

Rambutan is a performance modeling and analysis tool for understanding the behavior of asynchronous, task-based execution models.  It consists of a deeply-instrumented runtime that collects statistics during the execution of a task-based…
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Continuing the Scaling of Digital Computing Post Moore’s Law

The approaching end of traditional CMOS technology scaling that up until now followed Moore's law is coming to an end in the next decade. However, the DOE has come to depend on the rapid, predictable, and cheap scaling of computing performance to…
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CoDEx: Co-Design for Exascale

The next decade will see a rapid evolution of HPC node architectures as power and cooling constraints are limiting increases in microprocessor clock speeds and constraining data movement. Applications and algorithms will need to change and adapt as…

ExaCT

LBNL is a key member of the Combustion Co-Design Center (ExaCT). Our work represents a collaboration between applied mathematicians and computational scientists who have developed the Low Mach number combustion code (LMC) and computer scientists focused on performance optimization through auto-tuning and DSLs, performance modeling, and architectural simulation.

ExaSAT

Please see our main webpage here.  One of the emerging challenges to design HPC systems is to understand and project the requirements of exascale applications. In order to determine the performance consequences of different hardware designs,…

Characterization of DOE Mini-apps

The Computer Architecture Laboratory (CAL) will advance Exascale Design Space Exploration to develop energy efficient and effective processor and memory architecture R&D for DOE’s Exascale program.
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CAL: Computer Architecture Laboratory for Design Space Exploration

The Computer Architecture Laboratory (CAL) will advance Exascale Design Space Exploration to develop energy efficient and effective processor and memory architecture R&D for DOE’s Exascale program.
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Green Flash

Our researchers have proposed an innovative way to improve global climate change predictions by using a supercomputer with low-power embedded microprocessors, an approach that would overcome limitations posed by today’s conventional supercomputers.

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Publications

Automatic Translation of MPI Source into a Latency-tolerant, Data-driven Form

February 21, 2017

Perilla: Metadata-based Optimizations of an Asynchronous Runtime for Adaptive Mesh Refinement

November 17, 2016

BoxLib with Tiling: An AMR Software Framework

June 17, 2016

ExaSAT: An Exascale Co-Design Tool for Performance Modeling

May 1, 2015

Variable-Width Datapath for On-Chip Network Static Power Reduction

September 18, 2014

Variable-Width Datapath for On-Chip Network Static Power Reduction

September 18, 2014

The Role of Modeling in Locality Optimizations

August 12, 2014

Collective Memory Transfers for Multi-Core Chips

June 13, 2014

Abstract Machine Models and Proxy Architectures for Exascale Computing

May 16, 2014

Channel Reservation Protocol for Over-Subscribed Channels and Destinations

November 19, 2013

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