Scientific Computing Seminar

The classical microprocessor architecture offers great flexibility but imposes a performance penalty of about 100:1. A plan to reach very high performance levels must seek architectures with less of a penalty or accept less flexibility. We will discuss advanced architectures (PIM, vector, multi-architecture) and their ability to raise the limits of performance.

Conventional logic families offer high performance and high density in exchange for high power consumption, yet we will show that high power consumption will increasingly overwhelm the other factors over time. We will explain the physics limits on current logic (such as Landauer's limit and a reliability limit) and alternative logic families (such as adiabatic and reversible) that can exceed these limits -- although with effects that flow through to the programming model.

While transistors have a long history of success and considerable momentum for moving forward, some new research devices (quantum dots, super conducting parametric quantrons, Y junctions, and others) can offer multiple orders of magnitude performance increase over transistors when combined with the technologies above.

The advances discussed above show promise of reaching the Zettaflops level and above, yet the required changes in machine design will impose changes in the programming model. We will explain how thread count is likely to increase dramatically and how compilers may need to alter code to save power.