Scientific Computing Seminar

Date:

Friday, December 19, 2003

Time:

1:00pm-2:00pm

Location:

50A-5132

Seminar Speaker:

Costin Iancu
Future Technologies Group

Title:

Is there a Path to High Performance Reconfigurable Computing?

Abstract:

Field Programmable Gate Arrays (FPGAs) are hardware devices that, for a given application, offer performance superior to that of a general purpose processor (GPP) and almost comparable to the performance of an Application Specific Integrated Circuit (ASIC). Traditionally, FPGAs have been used with impressive performance results in the application domains of digital signal processing and data encryption.
While the performance advantages of using FPGAs in a general purpose computing system are widely recognized, their widespread use has been hampered by the lack of good software development tools and system integration. In the first part of this talk I'll present a short overview of the state of the art of the software development tools and directions of research conducted in this area.
Ease of programming aside, until very recently FPGA devices were not well suited for scientific computing applications due the high gate density required to implement double precision floating-point arithmetic. Current generation devices are dense enough to support a large class of single precision floating-point applications and according to industry projections, implementing double precision applications will become feasible from a price/performance point of view in late 2004/2005.

In the second part of this talk I'll cover the potential uses of FPGAs for scientific computing applications as: 1) hardware accelerators, 2) protocol accelerators, and 3) smart memory engines. When using FPGAs as hardware accelerators, part of the computation kernel of an application is compiled in hardware and executed on the attached FPGA device. In a protocol accelerator scenario, FPGAs are placed between the main processor and the Network Interface Card (NIC) and are used to offload parts of the computation directly following a data transfer. In the smart memory engine scenario, FPGAs are used as data transposition engines or address translators. This part of the talk will be focused on the performance limitations of the current systems architecture and the expected benefits of using recent interconnect (HyperTransport) and memory (Rambus) technologies.

Sponsor of Seminar:

Brent Gorda

Scientific Computing

Contact Esmond G. Ng EGNg@lbl.gov